- WeeBit ReRAM memory fits into chips without changing the existing transistor structures
- Each ReRAM cell stores data using resistive switching, not traditional flash methods
- ReRAM can handle between 100,000 and 1 million write cycles
Texas Instruments’ decision to license embedded ReRAM from Weebit Nano has reignited claims that flash memory has reached structural limits.
The agreement follows earlier deals with SkyWater, DB HiTek, and Onsemi, marking a steady escalation in manufacturing partners rather than an abrupt endorsement.
Weebit’s CEO, Coby Hanoch, told All About Circuits that the progression was deliberate, with each stage increasing both process scale and industry credibility.
Architecture choices and manufacturing friction
“We went up an order of magnitude each time,” he said. “From SkyWater to DB HiTek to Onsemi and now to TI. Now we’re in the major league.”
Weebit implements its ReRAM as a back-end-of-line module, allowing integration without altering front-end transistor structures.
This approach keeps additional wafer costs near 5%, compared with far higher overheads associated with embedded flash processes.
The memory cell itself relies on resistive switching instead of floating-gate storage, enabling bit-level access without block erase operations.
These design decisions are framed as pragmatic rather than revolutionary, relying on standard materials and conventional fabrication tools.
“We said from day one we would use standard materials, standard tools, standard flows,” he said. “We didn’t want to give fabs excuses not to work with us.”
From a specification standpoint, Weebit reports write speeds up to 100x faster than embedded flash, alongside endurance ranging from 100,000 to 1 million cycles.
The company reports that power consumption is lower due to reduced operating voltages and direct access modes.
Its CEO bluntly claims that “power, speed, endurance, temperature, and cost, on every axis that matters for embedded memory, ReRAM looks better than flash.”
The company also emphasizes immunity to electromagnetic interference, contrasting its technology with MRAM.
“We’ve seen cases where magnetic fields corrupted MRAM in consumer environments,” Hanoch said, adding that large manufacturers considered that risk unacceptable.
As process nodes shrink below 28nm, embedded flash becomes increasingly difficult to scale reliably.
Designers often compensate by pairing logic dies with external flash and staging data into SRAM at boot, increasing complexity and power draw.
Hanoch argues that non-volatile ReRAM removes this inefficiency, enabling instant boot and tighter security boundaries.
The greater density of ReRAM compared with SRAM allows edge devices to store more data on-chip, directly improving computation accuracy.
“More bits on the same silicon means better accuracy for inference,” he said, while also pointing to demonstrated neuromorphic experiments where “the ReRAM bit behaves like a synapse.”
Weebit cites industry forecasts projecting ReRAM revenue to grow about 45% per year, potentially reaching $1.7 billion within six years.
But its revenues remain modest, though rising, and the company attributes slower uptake to institutional caution rather than technical gaps.
“The biggest barrier is human nature,” Hanoch said, despite pointing to working silicon at multiple nodes and mass production qualifications.
Whether TI’s endorsement confirms that “ReRAM is the replacement for flash” remains to be seen.
Even so, the search for a universal memory remains unsettled, with alternatives such as ULTRARAM, developed by Quinas Technology, entering the field last year.
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